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ATM over SDH
Networking
The ATM Forum has defined SONET/SDH
interfaces, which involve the mapping of ATM cells into an SPE.
Cells are placed back to back, after the cell payload is scrambled
by a 1 + X43 self-synchronous scrambler. This scrambler
is in addition to the scrambler used in SONET/SDH. The scrambling
process is necessary to guarantee that the SONET/SDH signal will
have enough transitions to allow line rate clock recovery at the
receiver.
In order to
recover the cells at the receiver side ATM equipment relies on the
ATM header cyclic redundancy check (CRC). Namely, the SPE is
scanned, on a sliding 5-byte (ATM header size) window, and CRCs are
computed. When a match occurs, synchronization is established, and
the scanning stops. The next CRC is checked by jumping 53 bytes
ahead, assuming back-to-back cell placement. In case of mismatch, a
new synchronization scanning starts
Figure
2: A view of ATM over SDH networking
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